The present invention relates to integrated circuit (IC) protection circuits, and more particularly to a switched electrostatic discharge (ESD) ring for ICs with multiple power inputs to improve ESD protection and pin isolation.
ICs are subject to damage by ESD while they are being handled during testing, packing, shipping or assembly onto a printed circuit board (PCB). Static charge may build up on the IC package body, a human being or test/handling equipment and then discharge through one or more external pins of the IC thereby damaging the internal circuitry of the IC. Extra circuits are often added to the IC to mitigate this problem.
A simple known ESD network includes a first series of diodes each having their anodes connected to respective IC pins and their cathodes connected to the positive power (or voltage) supply pin. A second series of diodes are provided having their anodes connected to ground or the negative power pin and their cathodes connected to respective IC pins. It is noted that throughout this disclosure, reference to xe2x80x9cnegativexe2x80x9d power pins, voltages, voltage rails, terminals or nodes with reference to power-related pins includes ground pins depending upon IC configuration (e.g., the negative power pins may be or otherwise include ground pins). Thus, each pin is coupled between the positive and negative power inputs via a pair of ESD diodes. A voltage clamp, such as a Zener diode or the like, is also coupled between the positive and negative supply pins. The voltage clamp draws current when the voltage across it exceeds its threshold voltage level. When the IC is mounted to a PCB and powered on, each of the ESD diodes are reversed biased as long as the voltages on the pins are between the supply voltage. An ESD pulse that would otherwise cause any pin to rise significantly above the positive voltage rail or below the negative voltage rail (or ground) forward biases a corresponding ESD diode to protect the internal circuitry. When the IC is isolated and not connected to a power supply, an ESD pulse applied between any two pins activates two or more corresponding ESD diodes and the voltage clamp so that current flows directly through the pins to protect the internal circuitry.
The simple ESD network just described provides good isolation between respective pins. Noise from the power supply or ground, however, couples to any one or more of the pins and to the rest of the circuit connected to these pins. In this manner, the simple ESD network provides sufficient isolation from pin to pin, but does not provide sufficient isolation between the pins and the power supply terminals (positive and negative and/or ground). A potential solution is to use the ESD network with dedicated, quiet supply and/or ground pins.
Many circuits have multiple power inputs with a corresponding multiple of positive and negative supply pins. For example, the IC may include two different circuits, each with a corresponding power input, where each power input has a voltage pin and a ground or negative pin. The internal supply and ground buses may be noisy, so the use of a pair of dedicated ESD rings is commonly used. The dual ring ESD network is similar to the simple ESD network described above, except that the ESD diodes are connected between an ESD high bus line and an ESD low bus line (the buses forming the ESD rings). Also, the positive and negative power pins for the two circuits are coupled to the ESD high and low buses, respectively, in a similar manner. At least one voltage clamp is typically placed between the ESD high and low bus lines. Multiple voltage clamps may be used and placed in parallel at different locations in the IC to reduce the distance traveled by large ESD event currents. For example, two separate voltage clamps may be provided, one for each of the circuits, or four clamps may be distributed among the four corners of the IC, etc.
If the first and second power supply voltages are kept below the breakdown voltage of the clamp devices, the ESD high and low buses are ideally direct current (DC) open-circuited. AC currents and voltages can be coupled through the capacitances of the various ESD diodes and drive the ESD high and low buses. In practice, even for the DC case, diodes are not perfect DC open circuits and some leakage current is often present which causes the ESD high bus to be near one of the positive supply voltages and the ESD low bus to be near ground or a negative supply voltage. The conduction of ESD pulses is similar to that described for the simple ESD circuit described previously when the IC is not connected or not powered. The dual ESD ring configuration provides better isolation between any one or more of the signal pins and the corresponding power supplies, but provides relatively poor isolation between any two or more signal pins.
Radio frequency (RF) ICs, for example, often have multiple circuits and corresponding power inputs, such as separate power inputs for transmit and receive circuitry. For example, a half duplex RF communication system includes a radio that switches between transmit and receive modes of operation. RF ICs require a relatively high pin-to-pin isolation such as equal to or greater than 60 decibel (dB) isolation. The solutions previously described either do not provide the desired level of isolation between the pins or do not provide a practical solution. The dual ring configuration described above does not provide the desired isolation between pins. Additional dedicated supply pins used exclusively for the ESD high and low buses increase package size and cost and are not practical for many RF applications. For example, many RF applications are implemented on battery-powered portable and/or mobile units that require reduced cost, size, power usage and weight solutions and maximal operating efficiency. Larger packages have increased parasitics, which can decrease isolation and overall IC performance. Also, extra pins require additional external components, such as decoupling capacitors and the like, which significantly increases circuit layout area.
An electrostatic discharge (ESD) switch circuit for an integrated circuit (IC) with multiple power inputs according to the present invention improves pin-to-power isolation of the IC. The IC includes a plurality of positive power pins and a corresponding plurality of negative power pins (which may be ground pins, depending upon the configuration). The IC also includes an ESD ring network with a high ESD bus and a low ESD bus. The IC further includes a control circuit indicating one of several operational modes. The ESD switch circuit includes a first switch circuit that couples the high ESD bus to a first positive power pin in a first operational mode. The ESD switch circuit further includes a second switch circuit that couples the low ESD bus to a first negative power pin in the first operational mode. In this manner, the first and second switch circuits provide greater isolation in the first operational mode.
The first and second switch circuits may further disconnect the high and low ESD buses from the first positive and negative power pins, respectively, in a second operational mode. Such is advantageous, for example, when the first positive and negative power pins are employed to provide power during the second operational mode. The first and second switch circuits may further couple the high and low ESD buses, respectively, to the second positive and negative power pins, respectively, in the second operational mode. In the second operational mode, the first and second switch circuits may further disconnect the high and low ESD buses, respectively, from the second positive and negative power pins, respectively.
The first and second switch circuits may further disconnect the high ESD bus from the first and second positive power pins and the low ESD bus from the first and second negative power pins, respectively, when power is removed. In this manner, when the IC is powered down or otherwise disconnected from a circuit, normal ESD current conduction takes place, such as through ESD diodes and the voltage clamp to remove high voltage ESD pulses from the internal circuitry. If a third operational mode is employed, the first and second switch circuits may further couple the high ESD bus to the first and second positive power pins and the low ESD bus to the first and second negative power pins, respectively, in the third operational mode.
In one embodiment, for example, the IC is a half-duplex RF IC with a control circuit that indicates either transmit mode or receive mode. The control circuit may be employed, for example, to connect an antenna to transmit circuitry during transmit mode and to receive circuitry during receive mode. When the transmit circuit is active in the transmit mode, the switch circuit couples the receive circuit voltage supply pins to the ESD buses to improve isolation for the transmit circuit. Likewise, when the receive circuit is active in the receive mode, the switch circuit couples the transmit circuit voltage supply pins to the ESD buses to improve isolation for the receive circuit. Decoupled supply pins provide an excellent low impedance AC ground path. By coupling the ESD buses to a low impedance AC ground path, signals coupled to these buses are largely directed through the supply pin. This has the desired effect of reducing any coupling to other pins. It is noted, however, that the present invention applies to any number of power inputs and internal circuitry.
The first switch circuit may include a first switch that selectively couples the first positive power pin to the high ESD bus in the first operational mode and a second switch that selectively couples the second positive power pin to the high ESD bus in the second operational mode. The second switch circuit may include a third switch that selectively couples the first negative power pin to the low ESD bus in the first operational mode and a fourth switch that selectively couples the negative power ground pin to the low ESD bus in the second operational mode. In this manner, the switch circuit includes four separate switches, one for each power supply pin. More particularly, the first switch has a closed position to couple the first positive power pin to the high ESD bus in the first operational mode and an open position to disconnect the first positive power pin from the high ESD bus in the second operational mode or when power is removed. The second switch has a closed position to couple the first negative power pin to the low ESD bus in the first operational mode and an open position to disconnect the first negative power pin from the low ESD bus in the second operational mode or when power is removed. The third and fourth switches have open and closed positions that operate in a similar manner with respect to the second positive power and negative power pins.
In an alternative embodiment, the first switch circuit includes a multiple position switch having a first position that couples the high ESD bus to the first positive power pin when the IC is in the first operational mode, a second position that couples the high ESD bus to the second positive power pin when the IC is in the second operational mode, and a third position that disconnects the high ESD bus from either of the first and second positive power pins. The second switch circuit includes another multiple position switch with three positions that couples the low ESD bus to the first or second negative power pins when the IC is in the first or second operational modes, respectively, and a third position that disconnects the low ESD bus from either of the first and second negative power pins.
An ESD protection circuit for an IC according to the present invention includes a high ESD bus, a low ESD bus, first and second ESD clamp circuits and a switch circuit. The switch circuit selectively couples first positive power and negative power pins to the high and low ESD buses, respectively, when the second circuit is indicated as operationally active and selectively couples second positive power and negative power pins to the high and low ESD buses, respectively, when the first circuit is indicated as operationally active. The IC includes a control circuit that indicates which circuit is operationally active. The first and second ESD clamp circuits each comprise a plurality of ESD diodes that electrically clamp each IC pin to the high and low ESD buses. At least one voltage clamp may be provided that is coupled between the high and low ESD buses. The switch circuit includes multiple two-position switches or multi-position switches that operate in a similar manner as previously described as controlled by the control circuit.
An IC implemented according to the present invention includes a plurality of pins including a plurality of positive power pins and a corresponding plurality of negative power pins, a first circuit that receives power via the first positive power and negative power pins, a second circuit that receives power via the second positive power and negative power pins, a control circuit that indicates operational mode of the first and second circuits, an ESD network that includes a high ESD bus and a low ESD bus, and a switch circuit. The switch circuit selectively couples first positive power and negative power pins and second positive power and negative power pins to the high and low ESD buses, respectively, based on the operational mode indicated by the control circuit.
In a more particular embodiment, the IC is a radio frequency (RF) communication chip that includes a transmit circuit that is active in transmit mode and a receive circuit that is active in receive mode. In any of the embodiments, the switch circuitry or switches may be implemented with any type of electronic switching devices, such as transistors or the like. Bipolar transistors or MOSFETs are contemplated.
A method of providing ESD protection for the IC includes detecting an operating mode of the IC and coupling a second positive power pin and a second negative power pin to high and low ESD buses, respectively, when a first mode is detected. The method may further include disconnecting the second positive power pin and the second negative power pin from the high and low ESD buses, respectively, when a second mode is detected. The method may further include coupling a first positive power pin and a first negative power pin to the high and low ESD buses, respectively, when the second mode is detected. The method may further include disconnecting the first positive power pin and the first negative power pin from the high and low ESD buses, respectively, when the first mode is detected. The method may further include coupling the first positive power pin and the first negative power pin to the high and low ESD buses, respectively, and coupling the second positive power pin and the second negative power pin to the high and low ESD buses, respectively, when a third mode is detected. The method may further include disconnecting the first and second power and negative power pins from the high and low ESD buses when power is removed.